The semiconductor industry employs a wide variety of techniques to package integrated circuits. For example, one technique encapsulates an integrated circuit within molded plastic. Such a technique often is generically referred to as one type of “package level packaging.” The final packaged integrated circuit using this technique often has a footprint that is much larger than that of the integrated circuit. Accordingly, such a packaged integrated circuit has a relatively large area to attach many interface conductors, such as a ball grid array. Consequently, the integrated circuit has many input and output ports (e.g., many balls of a large ball grid array) for electrically communicating with other, external components.
Another technique protects the sensitive portions of the chip (e.g., exposed conductors) with a passivation layer that exposes certain conductors (e.g., electrical contacts). The exposed conductors of the integrated circuit can be processed for connection with external components (e.g., a printed circuit board). This latter technique often is generically referred to as one type of “wafer level packaging.” In a manner similar to the noted package level packaging technique, wafer level packaging typically has a limited footprint; namely, about the footprint of the integrated circuit. Accordingly, this type of package has less space to attach interface conductors, thus limiting the number of input and output ports for communicating with other, external components.